Delay Switch with OP Amp [Schematics + DSN]

Hey, Guys I have received a mail from one of my friend at 22 march about a Circuit Diagram. I mean, He has made a working Schematic of Delay Switch using OP Amp. I Know, There are lots of web Blog and Ton's of Schematic available for this particular Design. But This is the simplest on I have ever seen.

Now the Question is, how the design actually work ?

A very Short and Simple explanation, This Circuit got a Pulser (Produce digital HIGH & LOW Pulse) as Input and a LED to Show the Output Status.

    Initially, Everything is in OFF State and when pulse is given then it turn the LED ON for selected time period and then Goes OFF. The main Concept is that even if the Pulse Remain High then also LED will Goes OFF after a period of time.

NOTE : ON time can be customize by changing the value of Capacitor.

Now Here is the Mail Which I have Got......Let See, What Pranjal Saxena (My Friend) Says

I was searching for a circuit to produce a delay in my circuit to turn on a LED for a  short period of time when the output of the main logical circuit becomes high.
So, basically I needed a circuit which when given a continuous ON signal, makes the LED ON for a while.
All the circuits, I could find on the internet were using an impulse input using some push button or else and were making the output high for a short period of time since the button is released.
But I needed something, in which input should be a continuous HIGH and the output should be a timed HIGH.
So I designed a circuit for that.
In this circuit, when the logic generator is low the LED is OFF, but when the logic is made HIGH, the LED starts glowing but switches OFF after some time, while the logic generator remains HIGH.
In this the R1 and R2 make a voltage of 0.34 volt between them (potential divider), due to which voltage between R3 and R4 is 0.11(pot. divider again) so Vin+=0.11.
While voltage between R5 and R6 is 0.14(pot. div.), so Vin- or VRef=0.14.
Vref > Vin+   => output LOW
when the logic HIGH is given, voltage b/w R1 and R2 becomes 4.3 volts thus the voltage at Vin+ becomes 1.38 but the voltage at the Vref 'tends' to become 1.856 but it takes time for the voltage to reach that level, because of the capacitor. During this time only does the output remain HIGH.
   

Circuit Diagram :-

Delay Switch by Pranjal

So, One more thing I wanna add to this post is that if you have a better Design than this then Please post a comment below and Share among the Elex Idea Blog Reader.

Circuit Designed by "Pranjal Saxena"

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Download DSN File :-  Link

Note :- DSN File is accesible through Proteus. You can simulate the circuit in virtual environment.